`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:17:34 09/13/2011 
// Design Name: 
// Module Name:    CPU_Registers 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module CPU_Registers();

input clk;
input reset;
input reg_loc;
input en_write;
input en_read;
output reg_val;
input reg_val2;
input reg_loc2;

reg [15:0] regfile [0:15];

always @(posedge clk, posedge reset)begin

	if(reset)begin
		regfile[0:15] = 0;
	end
	
end
endmodule
